FPGA vs GPU acceleration for distributed shuffle operations: memory bandwidth and pipeline trade-offs

We have been running benchmarks on GPU acceleration for our Spark jobs and are hitting diminishing returns when joins and shuffles are involved. The memory bandwidth bottleneck appears to be the main issue rather than compute capacity. A few vendors are pitching FPGA-based approaches instead, arguing they can pipeline operations more effectively for Spark's specific operator patterns. From a hardware architecture standpoint, does this approach actually scale in production, or are we simply exchanging one bottleneck for another? Looking for technical insights on the trade-offs. submitted by /u/